The present invention generally concerns a scan/set testable latch constructed in Emitter Coupled Logic (ECL) or Current Mode Logic (CML) cellular gate array structures. The present invention specifically concerns the efficient construction of a scan/set testable latch from cellular gate array structures which are elsewhere utilizable in implementation of other logic macros. This commonality of the cellular gate array structures from which the fast, efficient, and scan/set testable latch of the present invention is constructed is a primary reason that such latch will have two levels of series gating. The present invention will specifically concern a fast scan/set testable latch using two levels of series gating which is efficient of implementation by virtue of being powered with one (only) current source, such creates efficiencies in silicon implementation. Such efficient implementation, and utilization of one only current source, will be obtained in the latch of the present invention because it will have a minimal number of indeterminate output states in respect of certain combinations of inputs, which combinations of inputs will, however, not be encountered when the latch is connected, as is intended, exclusively to logic macros likewise implemented in cellular gate array technology.
The purpose of the present invention is to provide a fast, efficiently implementable, scan/set testable latch circuit constructed of common cellular gate array structures used in digital logics, such as the logics of high performance central processing units. It is known in the prior art that such a latch should be fast in order to allow the logical functions implemented thereby such latch to transpire with maximum speed. It is further known that, because of the fact that approximately 30 to 50 percent of some digital logic designs, such as those of central processing units, are involved in latches and their supporting scan/set circuits, such latches should be efficient of implementation, utilizing a minimum of silicon area and a minimum of power.
The fast ECL/CML latch of the present invention is scan/set testable, and, indeed, may be considered to derive some of its efficiencies of implementation by the manner in which scan/set testing is performed by such latch. Scan/set testing is a well known prior art means of testing increasingly complex digital logics with their attendant increasingly difficult problem of thorough testing. As the gate-to-I/O pin ratio has continued to increase with new technologies, the ability to control and observe internal nodes of digital logic circuits has continued to decrease. Where the ratio of logic gates to I/O pins is large, as in very large scale integrated gate array technology, the utilization of the scan/set test technique greatly increases the testability of a logic circuit, allowing nearly 100% coverage of the contained gates. The scan/set test technique allows the internal registers of the circuit under test to be used as virtual I/O pins, thus reducing the logic gate-to-I/O pin ratio. This has the advantage of increasing the controllability of the digital logic circuit under test. The use of the scan/set test technique eliminates the requirement for manual generation of test vectors for digital logic circuitry. Manual generation of test vectors is very undesirable because of the excessive amount of designer time required, and because of the potential inadequacy of test coverage.
Scan/set testability in accordance with the prior art and with the present invention is implemented by the utilization of flip-flops, or latches, which have two data inputs: a parallel data input for normal operation and a serial data input for scan/set test operation. The selection between the two data inputs, between normal and scan/set data, is controlled by the distribution either of functional clock signals which do enable the usage of normal data (called System Mode of Operation), or by both scan/set clock plus scan/set test enablement signals which do enable the usage of scan/set data. The use of scan/set testable flip-flops, or latches, provides two major advantages. The first advantage is to allow the utilization of such flip-flops, or latches, during normal operation of the digital logic circuitry as latches or, combinatorially, as a functional register. The second advantage is to allow information to be shifted into the flip-flop (providing controllability) as well as allowing retrieval of information from the flip-flops (providing observability). The input function is termed "set" while the output shift is termed "scan". Both operations can be performed at once if the data to be input for the next test step may be anticipated while the output of the present step is being examined.
A scan/set testable flip-flop, or latch, functions in two modes under the control of separate system clock, or a scan/set test clock plus a scan/set test enablement. The two modes of operation are commonly called the System Mode and the Scan/Set Test Mode. In the Scan/Set Test Mode, the latch is used for the testing and maintenance of digital circuits, including Very Large Scale Integrated (VLSI) or Ultra Large Scale Integrated (ULSI) circuits. The same performance of the latch is not normally required, but within the prior art is normally offered, in the Scan/Set Test Mode as in the System Mode. Conversely, and more importantly, the performance of the latch in System Mode is often considerably less than would be obtained by a latch not incorporating scan/set testability because of the very inclusion of such testability, which will later be seen to add, within the prior art, either delay in series gating the latch and/or considerable extra capacitive load to the latch.
The present invention is implemented in gate array technology from common cellular gate array structures. The prior art gate array is a general utility chip design providing complete but unconnected multi-transistor cells, arranged in a regular matrix. The gate array leaves the interconnection of its transistors undefined, such interconnection to be determined at function design time by each designer, usually working with predefined functions on "books", and implemented in the mask levels which deposit the metallization layer interconnects. The argument for the gate array is that a gross reduction in lead time and cost may be obtained where a custom design is not feasible or cannot be justified on the basis of performance or size. The "internal" cell types are typically arranged in immediately abutting locations, in rows separated vertically by routing channels reserved for horizontal metal runs. Connection of the cell to the horizontal metal routes is achieved with polysilicon or metal routes that are part of the basic cell design projecting out into the horizontal channels. All internal cells are identical, and are within themselves laid out so that the specified number of interconnect paths may cross through them in the vertical direction. There is also a vertical routing channel on either end of the rows. The chip is personalized by etching connect points and laying down horizontal and then vertical metalization routes.
For gate array applications, a common cellular array construction consisting of a fixed set of electrical components, called a cell, must be used to efficiently implement various simple functions, such as NAND gates and invertors, as well as the scan/set testable latch function. A minimum cluster of components and/or interconnect that might be used in gate array technology to perform a logic function may be called a quarter cell. Such a quarter cell might typically minimally consist of nine transistors, five emitter followers, four inter-macro pull-down resistors, two level shifter pull-down resistors, two swing resistors, one TEE resistor, one glitch resistor, and one current source resistor. Other combinations are possible, such as stick layouts consisting of a few transistors and resistors per minimum building block. The macros or books are typically of fixed height and variable width. Each macro or book consist of one to many stocks or basic building blocks.
The pertinent concept is merely that the construction of a scan/set latch in gate array technology should be efficient in the utilization of those common cellular array structures which are elsewhere utilizable for the implementation of other primitive digital functions. For all such primitive functions, including the scan/set latch, the gate array interconnect is further used to connect these primitive functions into larger constructions, such as scan/set testable flip-flop pairs, and subsequently into macro functions like counters, registers, decoders, comparators, etc. Such macro functions called "books" constitute the "library" for an individual gate array type. Around the periphery of the gate array are located other cell types which are used for input/output, clock, or power regulation. The book in the library of a gate array are those functions which the gate array designer thought would be useful, and have been designed in anticipation of use. Libraries are augumented as users develop needs for other functions.
So recognizing that the prior art common cellular gate array structures, which common cellular gate array structures are utilized to implement the fast scan/set testable latch of the present invention, needs also be utilized to efficiently implement other combinatorial logic macros, the prior art implementation of scan/setable latches which utilize available components in too formal an emulation of the standard, logical-specification- type, bullet and shield representation of a scan/set testable latch. In other words, the controllable gating of scan/set test data onto a latch, thus making such latch scan/set testable, is normally logically represented by various combinations of AND, OR, and NOR gates occurring by various combinations of AND, OR, and NOR gates occurring in front of such latch. Particularly in the case of series gating, these equivalent AND, OR and NOR logic gate representations do not necessarily represent the equivalent gate delays. The logic designer who starts to implement his/her scan/set testable latch in emulation thereof such AND,OR and NOR logical functions is precluding himself/herself from identifying the most efficient overall implementation of a scan/set testable latch by failing to take a totally integrated view of the entire structure. In other words, the traditional and standard mode of logical representation by bullets and shields is an obstacle to envisioning the integrated construction of a scan/set testable latch.
In particular, one prior art implementation of a scan/set testable latch slavishly imitates the two levels of series gating which do allow scan/set or system data to be applied to such latch, and thus requires three current sources in implementation. In recognition that three current sources are not desirable on the grounds of efficiency in silicon implementation, another prior art scan/set testable latch has been implemented with but a single current source but which such scan/set testable latch then uses three levels of series gating. Such three levels of series gating, if implemented in gate array technology, must be accomplished with those identical common cellular gate array structures which needs elsewise be utilized for combinatorial logic macros. But very few, or none, of such macros require so many as three levels of series gating. Thus, the solution of the multiple current source inefficiency in the prior art by reversion to a scan/set testable latch circuit utilizing three levels of series gating is a poor solution. Some sort of comprehensive approach to the efficient implementation of a scan/set testable latch, such approach as is taken in consideration of speed of operation in gate delays and in consideration of silicon efficiency, as opposed to being guided by too rigorous a replication of the (arbitrary) logical standard representation thereof such scan/set testable latch, is seemingly called for.